Chip Level Library & Design Optimization Engineer
Company: Apple
Location: Beaverton
Posted on: September 20, 2023
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Job Description:
Summary Posted: Jan 11, 2023 Role Number:200451481 Do you love
building without precedent? As part of our Digital Design IP group,
you'll take imaginative and revolutionary ideas and determine how
to turn them into reality! You and your team will apply engineering
fundamentals and start from scratch if needed, bringing
forward-thinking ideas to the real world. Your efforts will be
groundbreaking! Join us in an exciting silicon design group that's
responsible for crafting innovative ASICs. You'll play an integral
role in designing the tools that allow us to bring customers
experiences they've never before envisioned. We have an
extraordinary opportunity in advanced process technology,
foundation IP (logic, memory) design, for implementation
pathfinding and optimization engineer. In this highly visible role,
you will be at the heart of a new advanced technology definition
for the future iPhone, Mac, watch processor design effort, working
with the custom digital circuits team and library development,
making a critical impact in delivering products to market quickly.
Key Qualifications A minimum of 10 years of experience in advanced
FinFet technology development (e.g. device, integration, process,
flows, EDA), circuit design, Semiconductor R&D Proven
understanding of advanced CMOS device behavior, with practical
understanding of device physics and analysis, and their impact to
SoC design PPA metrics Thorough knowledge and understanding of
yield (for a product or a technology learning vehicle), including
defect pareto development and Failure Analysis methodology,
Benchmarking practice Strong data analysis (and statistical
analysis) skills; proficiency with a broad set of data analysis
tools for both device and yield analysis Solid understanding to
perform basic circuit analysis, extraction, and SPICE simulation
for PPA benchmarking applications Great interpersonal skills to
champion initiatives internally and externally, for effective
communication with executive management and external partners
Technical, analytical, and multi-functional collaboration skills
Description Imagine yourself at the center of shaping the forefront
of advanced technology, custom IP offering that helps apple product
silicon performance, power stands-out. The selected candidate will
be part of a highly visible core team responsible for pathfinding
and validation of standard-cell (and block-level) DTCO boosters,
for better Power and Performance, in technologies with advanced
transistor architecture, with the goal of co-defining / optimizing
technology features & entitlements with foundry and research
partners. You will have the opportunity to integrate and come-up
with new insights, as well as work with a team of hardworking
engineers. As an Advanced technology path-finding and design
optimization engineer for the custom circuits, you will: - Be the
interface to internal Technology, Logic, Memory design teams, CAD
and PnR implementation team for planning production flows and with
foundry on PDK requirements - To analyze and interpret the result
of complex Power Performance Area (PPA) projections for logic,
memory, custom IP and block level design boosters - Define
strategies for IP design, considering trade offs in library
architecture/design, chip level PPA requirements, technology
interactions and metal stack optimizations - Collaborate with
technology team and foundry to define requirements to optimize
process for power, timing, area and yield for apple silicon designs
Education & Experience BS and a minimum of 10 years of relevant
industry experience Additional Requirements
Keywords: Apple, Beaverton , Chip Level Library & Design Optimization Engineer, Engineering , Beaverton, Oregon
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