Memory Subsystem Verification Engineer

Company: Apple
Location: Beaverton
Posted on: September 20, 2023

Job Description:

Summary Posted: Jan 9, 2023 Role Number:200451607 Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this highly visible role, you will be at the center of a chip design effort collaborating with all subject areas, with a critical impact on getting functional products to millions of customers quickly. Key Qualifications Minimum BS and 3+ years of relevant industry experience. Experience with digital logic design, CPU and SOC architecture/micro-architecture and memory subsystem is preferred Strong programming (C/C++, Verilog, Scripting), software optimization, and performance improvement skills Experience in unit and full chip level test benches Experience in developing testplans, assertions, and developing stimulus Should be a great teammate with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design Experience with emulation and developing synthesizable transactors is a plus Description * Play a critical role in end-to-end verification of memory subsystem by developing an in-depth understanding of cache coherence protocols and functioning of various units in CPU/GPU/SOC that are relevant to memory subsystem verification. These units include Load-Store unit, different levels of caches, bus interface units, memory controller, etc. * Develop verification environment which can be used in both simulation and emulation * Develop synthesizable transactors and test benches and support verification hooks for verifying memory subsystem functionality and CPU/SOC features * Develop unit level stimulus as well as full chip assembly programs to verify memory subsystem * Develop verification IPs * Work closely with the CPU, SOC, and GPU RTL design teams and understand the specification in detail for developing verification strategy for the above mentioned environment taking system level considerations into account * Develop coverage monitors and accomplish coverage goals * Debug failures in both pre and post silicon environments, root-cause problems, and propose design changes to address issues * Develop abstract end-to-end checks to verify CPU-SOC memory subsystem interaction and coherence protocols * Use novel techniques such as formal verification, emulation/FPGA technology, as well as industry standard tools and languages to verify memory subsystem Education & Experience Minimum BS and 3+ years of relevant industry experience Additional Requirements

Keywords: Apple, Beaverton , Memory Subsystem Verification Engineer, Engineering , Beaverton, Oregon