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SoC Physical Design Verification Engineer

Company: Apple
Location: Beaverton
Posted on: May 25, 2023

Job Description:

Summary Posted: Apr 13, 2023 Role Number:200474621 At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC. Key Qualifications Minimum BS and 3+ years of relevant industry experience. Strong knowledge of physical verification flows and methodology. Knowledge of all aspects of ASIC physical design. Scripting skills to debug flow related issues and make enhancements as appropriate. Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc. Real chip tapeout experience with a track record of successful signoff. Layout design background and experience a plus. Description * As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. * You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. * You will lead schedules and support cross-functional engineering efforts. * You will work on padring, bump, RDL design, and working with the package and floorplan teams. Education & Experience Minimum BS and 3+ years of relevant industry experience. Additional Requirements

Keywords: Apple, Beaverton , SoC Physical Design Verification Engineer, Engineering , Beaverton, Oregon

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